1. Field of the Invention
The present invention generally relates to integrated circuit test systems, and more particularly to a computer program that analyzes integrated circuit power supply pin quiescent current measurements.
2. Description of Related Art
Manufacturing tests and design verification tests are necessary for ensuring functionality and reliability of large-scale digital integrated circuits such as Very Large Scale Integration (VLSI) circuits. Millions of transistors and logic gates are often combined on a single die and the performance of the die is verified both in the design phase and the manufacturing phase of a VLSI product cycle.
Power supply current for individual gates or blocks within such a VLSI circuit combines to generate the power requirements for the overall die, and will typically combine in sub-groups to several power and ground pins that are typically also connected within the integrated circuit package. Faults within a VLSI circuit are generally caused by short circuit paths or open circuit paths in conductor or semiconductor segments and as device and line size is decreased in order to increase transistor count, a tolerable defect level is established by a manufacturer. Post-manufacture testing is performed, generally at the wafer level, in order to avoid packaging defective devices.
One test that has proven very efficient for determining whether short circuit faults exist in semiconductor dies is a quiescent supply current test (or IDDQ test). IDDQ testing is typically performed by measuring the leakage current through the power supply plane (sum of the power pin or return pin currents, i.e., IDDQ) using a manufacturing tester parametric (analog) measurement capability. A series of test vectors are used to exercise internal states of the integrated circuit and the IDDQ measurements are used to discover states in which an internal short is activated (for example, a short to ground on the output of an inverter raises IDDQ when the input of the inverter is set to a known low state by the test vector pattern).
However, typical logic gate signal transistors within present-day VLSI circuits have relatively high impedance, therefore the IDDQ rise caused by a short circuit may be slight, as a “perfect” IDDQ for the entire die may be very high for devices including millions of transistors and the additional contribution from a single short may be masked by measurement noise or die-to-die variations in IDDQ. The effect of a short on IDDQ may be different depending on the internal logic states set at particular vector. Additionally, the “background” IDDQ typically varies significantly as a function of the internal state of the die, masking variations that are indicating activated defects. Further, even for failure-free devices IDDQ measurements vary significantly between each vector and defects such as wafer defects may cause only a partial short circuit that may affect performance or reliability of a die, while causing only a slight change in IDDQ.
Due to the differing influences of a short on IDDQ mentioned above, variations in IDDQ due to activated faults tend to fall into discrete categories, or levels of IDDQ separated by gaps, that provide further information about the location and/or nature of a fault. In addition, there is a category of IDDQ levels that correspond to an absence of activated faults. For diagnostic purposes, it would be useful to identify a category of a fault generated by a short for a particular vector, via an IDDQ measurement. For diagnostic purposes, it would be useful to study the behavior of IDDQ over a large range of test vectors. However, in production testing, the number of IDDQ test vectors for which IDDQ measurements are collected is generally very limited, as IDDQ measurement is a time-consuming process. Further, the devices available for diagnostic analysis may only consist of defective devices, as yield may be low during a “bring-up” phase or because diagnostic data collection resources are reserved for use only on defective devices.
Techniques exist that establish per-vector thresholds for IDDQ measurements to attempt to compensate for the variations due to internal differences in states. However, such techniques typically do not condition data for diagnostic use that takes advantage of relationships between a defect, the internal state of the die as set at a particular vector and the IDDQ level of the die at the particular vector. In particular, the above-mentioned techniques typically do not assist in categorizing a fault/vector relationship for diagnostic purposes. Moreover, prior techniques typically rely on baseline data that is based on inclusion of a significant number of “good” devices in the sample.
Therefore, it would be desirable to implement an improved IDDQ testing algorithm that provides diagnostic information as well as improved pass/fail test information. It would further be desirable to provide an algorithm that takes advantage of relationships between a defect and the internal state of the die at each vector.